bridging hardware and software via object-oriented python and pyserial — demonstrated in the completed arduino data bridge project.
fpga logic / bare-metal firmware / quantum workflows
kuku dompreh
systems engineering student buildingfrom the silicon up
MEng Computer Systems Engineering at Warwick. Currently leading WQIG's build of an open-source, low-latency FPGA trading pipeline — on top of a summer spent shipping bare-metal ARM firmware and RTL projects from first principles, and a URSS-funded research internship in quantitative systems.
status: leading an active FPGA trading-hardware build. three projects shipped this year.
os ubuntu/linux target
stack verilog/c/python
mcu stm32 arm cortex
fpga tang nano 9k
active — hardware lead
hft tick-to-trade pipeline (wqig)
founded and lead a 3-person team building an open-source, ultra-low-latency l2 order book and fpga execution engine, backed by a £3,000 engineering grant. architecting the systemverilog data-path and axi4-stream ingestion now.
completed — view on github ↗arduino-to-python data bridge
engineered a serial pipeline from an arduino microcontroller to a threaded python oop class via pyserial, streaming live sensor data to a matplotlib telemetry dashboard.
completed — view detailstang nano 9k fpga uart pipeline
engineered a complete uart pipeline from first principles at rtl: a hand-derived verilog clock divider producing 115,200 baud from a 27mhz crystal, and a 4-state fsm verified race-condition-free in gtkwave — no vendor ip cores.
completed — view detailsstm32 bare-metal data logger
programmed an stm32f401re via direct memory-mapped i/o with no hal, configuring rcc/gpio registers and an nvic-driven isr to stream live adc samples to a matplotlib dashboard over pyserial.
about
engineering hardware from the inside out.
i'm a computer systems engineering student at warwick. instead of relying on high-level software abstractions and vendor libraries, my focus is on understanding how physics, digital logic, and firmware actually interact at the silicon level.
current objective
download cv
leading a 3-person team building an open-source, low-latency fpga trading pipeline through wqig, after a summer spent shipping bare-metal firmware and rtl projects from first principles — building toward the 2027 industrial placement cycle.
shipped a complete uart pipeline on a tang nano 9k — hand-derived clock divider and 4-state fsm at rtl, verified in gtkwave, no vendor ip cores.
shipped a hal-free stm32 data logger — direct memory-mapped rcc/gpio config and an nvic-driven isr streaming live adc data over pyserial.
currently architecting an fpga tick-to-trade pipeline for wqig — systemverilog data-path, axi4-stream market data ingestion, and c++ verilator co-simulation.
completed a urss-funded research internship at wmg — architected a c++ data-ingestion engine and tuned floating-point tolerances for quantum simulation datasets.
technical roadmap
- real-time embedded firmware
- hardware-aware algorithms
- telemetry and instrumentation
- quantum circuit workflows
modules
- computer organisation and architecture
- electrical and electronic circuits
- systems modelling and simulation
tools and equipment
- yosys / openFPGALoader
- gcc arm toolchain
- ni multisim / labview
- ubuntu 24.04 lts
- git / github
preferred problems
- deterministic scheduling
- hardware-software boundaries
- memory-mapped control
- digital logic synthesis
meng computer systems engineering
university of warwick, with focus across computer architecture, circuits, systems modelling, and simulation.
pathway undergraduate research scholarship (urss)
awarded independent research funding to investigate quantum algorithms and parametrised quantum circuits at warwick manufacturing group — beginning summer 2026.
arduino-to-python data bridge — shipped
first project completed and live on github: a serial telemetry pipeline connecting arduino hardware to a live python matplotlib dashboard.
stm32 bare-metal data logger — shipped
programmed an stm32f401re via direct memory-mapped i/o with no hal — nvic-driven isr, adc sampling, live matplotlib telemetry.
quantitative systems research internship — completed
wmg, urss-funded: architected a c++ data-ingestion engine and numerically stable pipelines for large-scale quantum simulation datasets.
tang nano 9k fpga uart pipeline — shipped
a complete uart pipeline built from first principles at rtl — hand-derived clock divider, 4-state fsm, verified in gtkwave, no vendor ip cores.
hardware lead, hft tick-to-trade pipeline (wqig)
founded and lead a 3-person team, backed by a £3,000 engineering grant, architecting an open-source low-latency fpga order book and execution engine.
build log
progress notes and system logs.
documenting the build pipeline across hardware projects, infrastructure setup, and research.
build pipeline
four systems. one active build.
three shipped this year — one live on github, two documented with waveform diagrams and build logs. the fourth, an fpga trading-hardware pipeline, is in active development as hardware lead for wqig.
research
investigations into hardware-efficient algorithms.
urss-funded research completed at warwick manufacturing group: parametrised quantum circuits and qaoa for combinatorial optimisation, with a focus on the c++ data-ingestion and numerical-stability engineering behind the simulation pipeline.
contact
direct channels.
for embedded systems conversations, research, internships, or technical queries, contact me directly.
availability
currently leading an open-source fpga trading-hardware project (wqig) while preparing for the 2027 industrial placement cycle. open to engineering and hardware systems opportunities.
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hidden lab
experimental interface layer.
prototype interactions for signal visualisation, shortcut-driven navigation, and personal lab notes.
uart telemetry mock
visualise incoming serial data streams for the upcoming python pipeline.
logic analyser skin
minimal waveform view inspired by gtkwave and embedded debugging sessions.
quantum circuit cards
compact gate-sequence previews for upcoming algorithm writeups.