bridging hardware and software via object-oriented python and pyserial — demonstrated in the completed arduino data bridge project.
fpga logic / bare-metal firmware / quantum workflows
kuku dompreh
systems engineering student buildingfrom the silicon up
MEng Computer Systems Engineering at Warwick. Building an independent hardware lab from first principles — open-source FPGA toolchains, bare-metal ARM drivers, and URSS-funded quantum algorithm research.
status: one project shipped. two planned for summer '26.
os ubuntu/linux target
stack verilog/c/python
mcu stm32 arm cortex
fpga tang nano 9k
completed — view on github ↗
arduino-to-python data bridge
engineered a serial pipeline from an arduino microcontroller to a threaded python oop class via pyserial, streaming live sensor data to a matplotlib telemetry dashboard.
planned — build pipeline (summer '26)tang nano 9k fpga uart pipeline
next sprint: designing a custom verilog clock divider and 4-state fsm on a tang nano 9k, bypassing ip cores to build a complete uart transmitter at rtl from first principles.
planned — build pipeline (summer '26)stm32 bare-metal data logger
next sprint: stripping the hal. decoding the reference manual to configure ahb buses and nvic hardware interrupts directly via memory-mapped c — no abstraction layers.
about
engineering hardware from the inside out.
i'm a computer systems engineering student at warwick. instead of relying on high-level software abstractions and vendor libraries, my focus is on understanding how physics, digital logic, and firmware actually interact at the silicon level.
current objective
download cv
executing a summer build sprint to master linux hardware toolchains, rtl design, and bare-metal firmware — building toward the 2027 industrial placement cycle.
building finite state machines, clock dividers, and digital logic from scratch using open-source yosys and linux toolchains — planned for summer '26.
bypassing the hal to manipulate memory-mapped registers, configure nvic hardware interrupts, and write lean c drivers — planned for summer '26.
urss-funded research into hybrid hardware-software workflows and nisq execution constraints at warwick manufacturing group — beginning summer '26.
technical roadmap
- real-time embedded firmware
- hardware-aware algorithms
- telemetry and instrumentation
- quantum circuit workflows
modules
- computer organisation and architecture
- electrical and electronic circuits
- systems modelling and simulation
tools and equipment
- yosys / openFPGALoader
- gcc arm toolchain
- ni multisim / labview
- ubuntu 24.04 lts
- git / github
preferred problems
- deterministic scheduling
- hardware-software boundaries
- memory-mapped control
- digital logic synthesis
meng computer systems engineering
university of warwick, with focus across computer architecture, circuits, systems modelling, and simulation.
pathway undergraduate research scholarship (urss)
awarded independent research funding to investigate quantum algorithms and parametrised quantum circuits at warwick manufacturing group — beginning summer 2026.
arduino-to-python data bridge — shipped
first project completed and live on github: a serial telemetry pipeline connecting arduino hardware to a live python matplotlib dashboard.
the hardware sprint
next: the tang nano 9k fpga uart pipeline and stm32 bare-metal data logger — engineering low-level hardware systems from first principles.
build log
progress notes and system logs.
documenting the build pipeline across hardware projects, infrastructure setup, and research.
build pipeline
three systems. one summer.
one completed and live on github. two planned for the summer sprint — cards will update with repository links, waveform diagrams, and build logs as each system moves from plan to physical hardware.
research
investigations into hardware-efficient algorithms.
urss-funded research at warwick manufacturing group into parametrised quantum circuits and qaoa for combinatorial optimisation — beginning summer 2026.
contact
direct channels.
for embedded systems conversations, research, internships, or technical queries, contact me directly.
availability
preparing for the 2027 industrial placement cycle. open to engineering and hardware systems opportunities.
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hidden lab
experimental interface layer.
prototype interactions for signal visualisation, shortcut-driven navigation, and personal lab notes.
uart telemetry mock
visualise incoming serial data streams for the upcoming python pipeline.
logic analyser skin
minimal waveform view inspired by gtkwave and embedded debugging sessions.
quantum circuit cards
compact gate-sequence previews for upcoming algorithm writeups.